- Publisert
- 2000
- Emneord
- Integrerte kretser
- Rapportnummer
- 2000/00138
- Permalenke
- http://hdl.handle.net/20.500.12242/1773
- Samling
- Rapporter
-
- 00-00138.pdf
- Size: 20M
- Sammendrag
- This report conlains a description of a floating-point adder optimized for throughput rather than latecy. It is confirmed with lEEE-754 standard for binary floating-point arithmetic. The design is fully tested and verified. Synthesis results for the A1catel Mietec MTC45000 technology are presented.