Improved Passivation Effect Due to Controlled Smoothing of the CdTe-HgCdTe Interface Gradient by Thermal Annealing

Haakenaasen, Randi
Selvig, Espen
Heier, Anne Cathrine
Lorentzen, Torgeir
Trosdahl-Iversen, Laila
Date Issued
Infrarøde detektorer
Haakenaasen, Randi; Selvig, Espen; Heier, Anne Cathrine; Lorentzen, Torgeir; Trosdahl-Iversen, Laila. Improved Passivation Effect Due to Controlled Smoothing of the CdTe-HgCdTe Interface Gradient by Thermal Annealing. Journal of Electronic Materials 2019 ;Volum 48.(10) s. 6099-6107
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HgCdTe films grown by liquid phase epitaxy were passivated with CdTe grown by molecular beam epitaxy. A series of annealing tests with different temperatures and durations were then carried out in order to reach a two-fold goal: to smooth the gradients in Hg and Cd content across the HgCdTe film-passivation interface, and to create a Hg vacancy concentration of ∼ 1–2 × 1016 cm−3. We want the composition gradient to prevent minority carrier electrons from reaching the actual interface, as this may contain recombination centers that trap the electrons. Four different temperature–time combinations were tried for the first part of the annealing procedure (the smoothing of gradients), while they were all followed by a Hg vacancy procedure of 250°C for 18–24 h. Then some samples were cleaved, and energy-dispersive x-ray spectroscopy (EDS) line profiles were recorded on the cross sections to monitor the composition gradients. We could clearly see differences between the profiles from samples with the higher-temperature annealing, the lower-temperature annealing and no annealing. Secondary ion mass spectroscopy profiles on two samples verified the EDS results. On another subset of similar samples, planar diodes were processed and resistance-area (RA) values determined. The current–voltage (I–V) curves from the high-temperature annealed samples seemed dominated by leakage current and did generally not display diode characteristics. This could be explained by their EDS profiles, which showed a lot of Hg in the entire passivation layer. The EDS profiles from the three low-temperature annealing procedures were very similar, but planar diode I–V curves revealed diodes of varying quality, and their RA values were used to differentiate among them. The optimal annealing procedure was 300°C for 4 h, followed by 250°C for 24 h.
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